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 F-RAM Technology and Products |
| F-RAM Parallel Memory |
Q: What are parallel F-RAM devices?
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A: Standard asynchronous SRAMs have been available in the market for many years. The interface is the simplest, and it is the type of memory that most designers think of when referring to “RAM.” It has a few control pins (/CE, /WE, /OE), an address bus, and a data bus. Ramtron offers x8 and x16 parallel parts. |
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Q: Why use a parallel F-RAM?
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A: Today, Ramtron offers x8 (bytewide) and x16 (wordwide) memory devices. Traditionally SRAMs have been used in systems that use a x8 memory. Speed is an advantage of a parallel memory device over serial parts. All address lines are presented at once and an access can start immediately. Data is transferred into and out of the memory 8- or 16-bits at a time. |
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Q: Does /CE need to toggle for every access?
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A: No, the newer devices (1Mbit and higher density) have ATD which allows the memory to access any location by simply changing the address. This feature is called Address Transition Detection and allows /CE to remain low. It is true that the 64Kb and 256Kb devices require /CE to toggle. |
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| F-RAM Processor Companion |
Q: Why doesn’t the RTC/oscillator run? Why is the RTC running slow? It seems that I have everything connected properly on my board, however I cannot activate the RTC with the crystal.
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A: Check that your board layout is clean - do not route switching signals next to the X1/X2 pins and be sure to have a guard-ring around the X1/X2 pins. Typically if the crystal pins are being disturbed by nearby switching signals, you will observe the CAL output is much lower than 512 Hz. Other things to check: be sure to remove solder flux near crystal pins, replace the crystal, initialize all battery-backed registers to a value within its valid range. |
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Q: What is the Ibak current when I insert a battery and Vdd is off?
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A: When a battery is first attached to the FM31xx while Vdd is powered off, there are a number of registers inside the chip that come up in an unknown state. These circuits are connected to the internal power supply. It is possible that the Ibak current is a few microamps or as much as 100 microamps. It's a random startup condition. Once Vdd is applied, the Ibak current goes to zero. All internal circuits are set to known states. When Vdd is then powered down, the Ibak current is < 1uA. This issue has been resolved on the FM3127x, FM31L27x, FM33xx, FM3130, and FM3135 devices. |
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Q: How long will a backup supercap last after a power loss?
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A: Using a 1F supercap, the RTC will operate for approximately two weeks. |
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Q: How much time will it take to charge up a supercap?
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A: A: The FM3130, FM3135, FM3127x, FM31L27x, and FM33xx have a fast charge mode. If a 1F supercap has been discharged to 1.5V, it will take approximately 30 minutes.
See also: AN404 – RTC Backup and UL
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| F-RAM Serial Memory |
Q: What are serial F-RAM devices?
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A: For many systems that are cost sensitive or space-constrained, it is important to design with physically small ICs and/or few chip-to-chip wires. Two-wire (I2C) and SPI devices satisfy these needs. The two-wire protocol that uses clock and data, was developed by NXP/Philips in the 1970s and is still very prevalent today. SPI devices are known as a three-wire interface, /CS, clock, and data, however “data” is comprised of two pins. A data input and data output. Most systems that use SPI devices have a four-wire interface. SPI devices operate at a higher clock frequency and therefore offer higher data rates. |
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Q: Why use I2C over SPI, or vice versa?
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A: Two-wire (I2C) is the most common and many micros implement a two-wire dedicated port. SPI operates at much higher clock rates, up to 20MHz. For simplicity and the use of fewer I/O micro pins, two-wire is generally used. |
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Q: How do I tell which density F-RAM device I have without looking at the part marking?
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A: You can write a known value (such as FF) to addresses 00h, 800h, and 2000h, then write data 11h to address 800h and do a read to address 00h. If you read 11h, then you know it is a 16Kb part. If you read FFh, then you can continue to the next boundary. Write data 22h to address 2000h and read address 00h. If you read 22h, then you know it is a 64Kb part. If you read FF, then it is a 256Kb device. You can apply this scheme to both I2C and SPI families. |
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| General F-RAM Product FAQs |
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| General F-RAM Technology FAQs |
Q:
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A: Please see the F-RAM technology timeline on our History page. |
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Q:
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A: F-RAM is commercially proven in the semiconductor market with over 150 million units sold. In addition, F-RAM uses much less power while operating and cannot be affected by external magentic fields.
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Q:
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A: Ramtron has formed strategic product licensing and/or manufacturing alliances with several large firms including Texas Instruments, Fujitsu, Toshiba, Samsung, Hitachi, NEC, Rohm and Samsung. Currently Fujitsu, is our primary foundry and we recently announced a manufacturing agreement with Texas Instruments for high-density F-RAM products.
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Q: What is F-RAM?
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A: F-RAM is a nonvolatile memory device that can hold data even after it is powered off. F-RAM is an acronym for ferroelectric random access memory. F-RAM is not ferromagnetic as there is no ferrous material (iron) in the chip. Ferroelectric materials switch polarity in an electric field, but are not affected by magnetic fields.
See also: Ferroelectric Technology Brief and What is F-RAM.
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Q: Are F-RAM devices affected by magnetic fields?
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A: F-RAM devices are ferroelectric memories and are not ferro-magnetic. They are not affected by external magnetic fields.
See also: F-RAM Technology Brief
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Q: Is FeRAM the same as F-RAM?
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A: Yes. FeRAM and F-RAM are synonymous. Ramtron does not hold a trademark on the word “F-RAM”. It may be freely used without restriction. |
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Q: What are the key advantages over EEPROM and Flash?
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A: 1) Speed. The “RAM” part of the F-RAM name tells us that it is a RAM, not a ROM. Of course, EEPROM and Flash are not truly ROMs but writing to them can be very slow. An F-RAM’s write cycles are completed immediately whereas an EEPROM/flash needs 5 to 10 ms.
2) Low Power Writes. Writes to the F-RAM cell occur at low voltage and very little current is needed to change the data. With EEPROM and Flash, high voltages (10V charge pump) are needed and writes require 5 ms to complete a page buffer write. The energy needed is much higher than F-RAM writes. If E=P*t, then 5ms of write time will necessarily require 200x more energy than F-RAM.
3) High Endurance. Writes are destructive – and floating gate devices eventually wear out; typical endurance is 100,000 to 1 million cycles. F-RAM experiences 1E12 read/write cycles or greater.
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Q: How large of an electric field can a F-RAM device withstand?
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A: The F-RAM memory cell operates by applying a switched voltage to sense and restore the data state. The ferroelectric film PZT is about 2000 A (0.2 um) thick. If the device is placed in a 50 kV field at 1 cm, it is not possible to produce more than 1V across the ferroelectric film. As a practical matter, F-RAM devices are impervious to external electric fields. |
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Q: Is F-RAM affected by radiation or soft errors?
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A: Volatile memories, DRAM and SRAM, use a capacitor to store charge or a simple latch to store state. These cells can be easily upset by a alpha particles, cosmic rays, heavy ions, gamma, x-rays, etc. which cause bits to flip to an opposite state. This is called a soft error, since a subsequent write will be retained. The rate at which this occurs is called the Soft Error Rate (SER) of the device. Because the F-RAM cell stores the state as a PZT film polarization, an alpha hit is very unlikely to cause the polarization to change a given cell’s state. The F-RAM terrestrial SER is not measurable. |
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Q: Are the new lead-free “green” packages (suffix -G) compatible with my existing leaded solder process?
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A: Lead-free devices (-G) can be used in a standard Sn/Pb solder process. The standard part (-S) cannot be used in a lead-free solder process.
See also: Environmental Technical Paper
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| I2C Interface |
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| SPI Interface |
Q: Why can’t I get SPI writes to work?
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A: You must issue a WREN opcode before the WRITE opcode. The WREN opcode requires the /CS pin to go low, clock-in the opcode (06h), then /CS must return high. The WRITE opcode then follows. The /CS pin goes low, clock-in the opcode (02h), clock-in the address (1 or 2 bytes), clock-in the data (1 or many bytes), then /CS must return high.
See also: AN304 SPI Guide
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| Support |
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| Versa 8051 MCUs |
| I²C Interface |
Q: Can the I²C interface operate in slave mode?
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A: Yes, the VRS51L2070/3xxx can operate in both master and slave mode. It is also possible to configure the I²C device ID. |
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Q: How fast can the I²C interface communicate?
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A: The I²C interface can communicate up to Fosc/32. When the VRS51L2070/3xxx operates from the 40MHz internal oscillator, the I²C interface can run up to 1.25Mbps. |
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Q: Is the I²C speed adjustable?
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A: Yes. Communication speed on the I²C interface is controlled by an 8-bit register. This provides a wide adjustment range, enabling the user to optimize the I²C communication speed to specific I²C bus characteristics, such as length or number of devices connected to it. A longer I²C bus requires a lower communication speed. For example, if the VRS51L2070/3xxx operates from the 40MHz internal oscillator, the I²C interface communication speed is adjustable from 4.8KHz to 1.25MHz. |
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| Flash and SRAM Memory |
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